In order to perform data transmission between different semiconductor devices, an I2C interface, a serial peripheral interface (SPI), or the like is used.
FIG. 1 is a diagram illustrating a transmission system using an SPI. A transmission system 100 includes a master device 110 and a slave device 120.
The slave device 120 includes a register 122 and an internal circuit 124. The register 122 is connected to be accessible from the internal circuit 124, and operates by referring to data stored in the internal circuit 124 or writes data or a flag obtained as a result of processing in the register 122.
The master device 110 and the slave device 120 are connected via a 4-wire interface, i.e., a slave selection enable (SSEN) line, a serial clock (SCK) line, a serial data input (SDI) line, and a serial data output (SDO) line. The master device 110 can write data to an address specified by the register 122 or can read data from an address specified by the register 122.
If the data is erroneous due to noise or the like during the writing of the data from the master device 110 to the register 122, the internal circuit 124 malfunctions due to the erroneous data. Therefore, in order to improve the reliability, a method called readback is used. Specifically, a series of processing is performed as follows:
(i) Write data to an address in a register
(ii) Read data from the same address in the register
(iii) Determine whether or not the write data matches the read data
(iv) When an error is detected, rewrite the same data.
FIG. 2A and FIG. 2B are timing charts of data writing and data reading.
Referring to FIG. 2A, in the data writing, the master device 110 selects one slave device 120 by setting the SSEN line to a predetermined level (here, low). Then, the master device 110 supplies a command (OP7: OP0) indicating a write operation, an access destination address (AD23: AD0), and write data of subsequent n words (where n is a natural number) (WD17: 10, WD27: 20, . . . , WDn7: n0), from the serial data input (SDI), in synchronization with a serial clock SCK.
Referring to FIG. 2B, in the data reading, the master device 110 outputs a command indicating a read operation, an access destination address AD, and dummy data together with the serial clock SCK. Then, data RD at a specified address is output from the serial data output (SDO).
As a result of reviewing the conventional data readback, it has been recognized the following problems. In the readback of the conventional interface, the read sequence illustrated in FIG. 2B occurs after the write sequence illustrated in FIG. 2A is completed. Therefore, there was a problem that a long time is required for determination by the readback. This problem is more pronounced in burst write in which a plurality of words are continuously written.
In addition, the internal circuit 124 may refer to the data written in the register 122 without waiting for verification on the host side. Therefore, if the data is erroneous after completion of the data writing, the internal circuit 124 malfunctions due to the erroneous data.